1. Technical Field
The invention relates to an integrated circuit arrangement having a substrate and having at least three directly successive conductive structure levels.
2. Description of Related Art
The substrate of a circuit arrangement is, in particular, a monocrystalline semiconductor substrate or a so-called SOI substrate (silicon on insulator). The conductive structure levels are also referred to as metalization levels because the conductive structures which they contain usually comprise a metal or a metal alloy, for example an aluminum alloy with an aluminum proportion of greater than 60 atomic percent or greater than 90 atomic percent of aluminum, or a copper alloy with a copper proportion of greater than 60 atomic percent or greater than 90 atomic percent. However, other materials are also suitable for the conductive structures, for example doped semiconductor material.
In the case of the conductive structures, distinction can be made between interconnects for lateral current transport and so-called vias or contacts serving for vertical current transport. In this case, vertical denotes a direction lying in the direction of the normal to a main area of the substrate in which integrated semiconductor components are also arranged. Alternatively, vertical means a direction opposite to the direction of the normal. Lateral means in a direction lying transversely or at an angle of 90° with respect to the direction of the normal.
The conductive structure levels each contain a multiplicity of conductive structures arranged in a level or a plane. Thus, modern planarization methods, such as the CMP method (chemical mechanical polishing), for example, produce essentially planar interfaces between the conductive structure levels. However, the designation of a conductive structure level may also be employed when the planarization is not completely planar in the context of the production tolerances. The individual levels can be distinguished from one another by other structural features, for example by particular interlayers between conductive structure levels or by specific distances between the level bottom areas and the substrate main area. In this case, the differences in the specific distances for different levels are at least twice as great or at least three times as great as the manufacturing tolerances for the spatial position of the bottom areas of the conductive structure level in which the interconnects with said bottom areas are arranged.
The conductive structures each contain at least one bottom area near to the substrate and a top area remote from the substrate. A direction of the normal to the bottom area lies counter to the direction of the normal to the substrate main area. A direction of the normal to the top area lies in the direction of the direction of the normal to the substrate main area, that is to say the area containing the semiconductor components, for example transistors.
The top areas of the conductive structures of one of the conductive structure levels in each case lie in a level top area of the conductive structure level. The level top area is a plane, for example. The bottom areas of the conductive structures of one of the conductive structure levels in each case lie in a level bottom area of the conductive structure level. The level bottom area is likewise a planar area, for example. Deviations from a planar level top area or a planar level bottom area arise for example as a result of the intermeshing of conductive structures of adjacent conductive structure levels.
Between the level top area and the level bottom area of a conductive structure level there is no intermediate area in which top areas or bottom areas of conductive structures of said conductive structure level are arranged. Accordingly, conductive structures produced by means of the dual damascene technique, in particular, are arranged in different conductive structure levels. In addition, conductive structure levels are produced by using the single damascene method or a so-called subtractive method, in which electrically conductive material is removed again during patterning from the conductive structure level to be produced, such as an RIE method (reactive ion etching), for example. The levels or planes in which the conductive structures of a respective conductive structure level are arranged preferably lie parallel to the substrate main area and thus also parallel to one another.
What is typical of known metalizations or wirings is the alternative use of a via level, exclusively containing vias, and an interconnect level, containing interconnects and, if appropriate, also vias or so-called landing pads. This arrangement is exclusively used in particular in inner conductive structure levels of the circuit arrangements.
The electrical properties of the metallization layer of the known technology if improved could open novel applications. Therefore, there is a need for an integrated circuit arrangement having a metallization layer with improved electrical properties.